The invention relates to the general field of integrated circuits with particular reference to FET gates and methods to operate them at lower voltages.
As part of the general development of integrated circuits there has been a steady drop in operating voltages. This has included a corresponding drop in the gate voltages used with Field Effect Transistor (FET) devices. FIG. 1 is a schematic illustration of an FET gate. Shown there is silicon substrate 11 on whose upper surface is a gate pedestal made up of silicon dioxide layer 15 and gate electrode 12. The above-mentioned reduction in gate voltage has meant that the thickness of the gate dielectric 15 has had to be similarly reduced. For traditional gate insulation made of silicon dioxide, this has meant gate dielectric thicknesses less about 15 Angstroms. When thicknesses get this low, dielectric leakage and premature breakdown become major problems.
To circumvent problems of this type, the FET art has begun using dielectrics having higher dielectric constants than silicon oxide. Since the charge density at the dielectric-silicon interface is proportional to the dielectric constant, thicker gate insulation can, in principle, then be used without otherwise affecting performance.
Among the dielectrics being considered as replacements for silicon oxide we include aluminum oxide and zirconium oxide. It has turned out that these materials, as normally deposited (e.g. by CVD (chemical vapor deposition)) result in devices with very poor high frequency performance whose cause has been identified as due to trapped charges in the dielectric.
The present invention describes how such charge can be permanently neutralized without introducing major changes into the overall device fabrication process. The principle on which the present invention is based is the observation that nitridation of a silicon oxide layer causes a shift of the flat band voltage to more negative values, as illustrated in FIG. 2 (where curve 21 is for NMOS devices and curve 22 is for PMOS devices). The flat band voltage is the minimum that is observed in a plot of capacitance as a function of voltage and the shift to more negative voltages is an indication that trapped positive charge has been introduced into the dielectric layer.
A routine search of the prior art was performed with the following references of interest being found:
In U.S. Pat. No. 6,251,761, Rodder et al. show a high K gate dielectric. A nitridation process is then used to convert the upper portion of the dielectric to a nitride. This is followed by an optional anneal. U.S. Pat. No. 3,978,577(Bhattacharyya et al.) shows an Aluminum oxide gate dielectric. U.S. Pat. No. 6,251,729(Montree et al.) shows an aluminum oxide inter-gate dielectric while U.S. Pat. No. 6,048,769(Chau) and U.S. Pat. No. 6,228,721(Yu) show related processes.
It has been an object of at least one embodiment of the present invention to provide an FET gate capable of operating at low voltages and having a minimum of trapped charge in the dielectric portion.
Another object of at least one embodiment of the present invention has been to provide a process for manufacturing said FET gate.
Still another object of at least one embodiment of the present invention has been that said process be fully compatible with current semiconductor device manufacturing practices.
These objects have been achieved by employing a high K dielectric such as aluminum or zirconium oxide. As deposited, this layer has a high density of trapped charge which is then neutralized by impregnating it with between about 5 and 10 atomic percent of nitrogen. Several methods for introducing the nitrogen are described. These include diffusion from an overlay of silicon nitride, diffusion from a gas source, remote plasma nitridation, and decoupled plasma nitridation.